There are numerous semiconductor process steps involved in the development of modern day integrated circuits (ICs). From the initial fabrication of silicon substrates to final packaging and testing, integrated circuit manufacturing involves many fabrication steps, including photolithography, doping, etching and thin film deposition. As a result of these processes, integrated circuits are formed of microscopic devices and wiring amid multiple layers.
In so-called "front end" processes, basic electronic devices, such as transistors and capacitors, are formed in and over a semiconductor substrate. "Back end" processes involve electrically connecting devices with contacts and wires integrally formed in the chip, in patterns dictated by circuit design. During the back end processes, conductive layers are separated from each other by insulating layers or interlevel dielectrics (ILDs). Contacts extend through ILDs to electrically connect overlying and underlying conductive layers. Typically, contact openings or vias are patterned and etched in the ILDs, such as by photolithographic and etch processes. Conductive material then fills the contact vias to complete the contact.
In conventional metallization, a layer of metal is deposited over an ILD with contacts already formed therethrough. A mask is then formed over the layer of metal, and parts of the metal are etched through the mask to leave metal lines in a desired pattern. Spaces between the metal lines are then filled with an insulator (e.g., a form of silicon oxide) and the insulator is polished or otherwise etched back to leave a planar surface. Damascene patterning conversely involves forming the insulator or ILD, etching a pattern of trenches into the ILD, where the trenches are shaped in a desired wiring path and depositing metal into the trenches. Excess metal overlying the ILD is then polished back to leave wires isolated within the trenches. Similarly, in dual damascene processes, contacts and wiring layers are simultaneously formed. In addition to forming the trenches of the above-described damascene process, contact vias or openings extend from the bottoms of those trenches prior to the deposition of metal. As metal fills the trenches and vias, contacts and wires are simultaneously formed.
Today's market demands more powerful and faster integrated circuits. In pursuit of such speed and lower power consumption, device packing densities are continually being increased by scaling down device dimensions with each progressive generation of integrated circuit design. To date, this scaling has reduced gate electrode widths to less than 0.25 .mu.m. Currently, commercial products are available employing gate widths or critical dimensions of 0.18 .mu.m or less.
As the spacing between devices on the substrate shrinks to obtain high density integration, lateral dimensions of metal wires or interconnect layers, as well as the contact holes and the via holes, are commensurately scaled down. However, due to reliability and parasitic capacitance concerns, there is a limit on shrinking the thickness of the interlevel dielectric (ILD) layers. The resultant vias exhibit increasingly high aspect ratios (the depth divided by width), introducing numerous problems for chip fabrication.
Dry etch processes, particularly reactive ion etch (RIE), advantageously result in vertical via walls, enabling high packing density. Energetic ions vertically impinge upon a masked substrate and etch holes or vias through openings in the mask. The resulting vias, however, are left with an organic residue, often referred to as a polymer, on the sidewalls of the holes. This polymer needs to be thoroughly cleaned to avoid contamination of the contact to be formed and to obtain good electrical interconnection between conductive layers.
Cleaning processes that effectively remove the polymer tend also to attack the materials surrounding the vias, such as the dielectric walls defining vias through ILD's. While a slight etch of the via walls advantageously undercuts the polymer and aids in its removal, overetching of the via walls can lead to short circuits and parasitic capacitance across closely spaced adjacent contacts. Such overetching can similarly produce a lack of precise control over feature dimensions during etching in a variety of different contexts in semiconductor fabrication.
Accordingly, a need exists for methods of strictly controlling etch processes, such as polymer cleaning from an opening after dry etch.